ASIC Verification

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• What is Functional verification ?
• What is Gate-level simulation ?
• Verification Issues
• ASIC Verification flow

Why verification is important?

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• Importance of verification
• Why verification is complex?
• When is verification complete?

ASIC Verification methodology

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• Verification environment
• Verification Terminology
• Test Bench Design
• Best Practices
• Randomization
• Automation
• High level languages
• Methodologies
• Methodology history
• Details on different methodologies

ASIC Verification coverage concepts

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• Functional coverage
• Code coverage
• Line Coverage
• Conditional Coverage
• Toggle Coverage
• Expression coverage

Basics of System-Verilog

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• Data types,
• Data Arrays, Dynamic Arrays, Associative Arrays
• Queues, System Functions
• User-Defined Data Types
• Enumerated Types
• Procedural statement and Routines
• Operators
• Subroutines (tasks & functions)

Fundamentals of OOP

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• OOP-Object oriented programming
• Terminology, Program Constructs
• Encapsulation, Inheritance, Polymorphism

Integration of Test Bench & DUT

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• Interfaces
• Mod ports
• Clocking blocks
• Stimulus Timing
• Transactors

Randomization

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• Differences b/w Randomization & Directed
• Constraints & it’s derivatives
• Pre & post randomization
• Random control constructs

Concurrency & Inter-process communications

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• Events
• Trigger constructs
• Fork-join constructs
• Semaphores
• Mailboxes

Functional Coverage

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• Basics
• Why functional Coverage?
• Coverage bins
• Cover points & cover groups
• Coverage reports
• Cross coverage

Advanced Concepts

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• OOPs
• Factory Patterns
• Call backs & its derivatives
• Virtual Interfaces
• Unions & Structures
• Direct Programming Interface like C,C++
• Environment Creation using SV
• Connecting DUT,TB & Third-Party BFM’s
• Tests creation using SV
• Checkers & Monitors

System verilog Assertions

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• Basics
• Concurrent Assertions
• Immediate Assertions
• Assert constructs
• Sequences
• Repetitions & Examples
• Sampled Value functions
• Coverage for Assertion

UVM Overview

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• UVM Testbench and Environment
• Interface UVC’s

UVM Library Basics

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• Library base classes
• uvm_object class
• uvm_component class
• UVM Factory
• Phasing

TB components

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• TLM port communication
• Virtual sequences
• Callbacks
• scoreboards
• Coverage models
• Stimulus Generation
• Macros
• Policies
• RAL (Register Abstraction Layer)

Test Bench Integration

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• Test benches and Tests
• Test bench class
• Test class
• Creating TB

Instantiating UVC’s in test bench

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• The Virtual sequencer
• Test bench configuration
• Creating a Test
• Checking for DUT data path check

Creating a scoreboard

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• Implementing a coverage model
• Selecting a Coverage Method
• Implementing a Functional Coverage model