Introduction

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• Analog and Digital signals.
• Digital circuits v/s Analog circuits

Logic Gates and Combinational Circuits

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• Truth tables of logic gates & representations
• Universal logic gates
• Combining gates to form circuits for simple logic functions.
• Code Converters
• Adders, subtractors and carry look ahead adders
• Multiplexers and design based on multiplexers
• Encoders and Decoders
• Parity Generators and Checkers

Sequential Circuits

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• Latches, Flip-flops
• JK, SR, D and T Flip flops and conversions
• Clock, setup time, Hold time
• Metastability Conditions and preventive actions
• Memory elements
• FIFO component

Design of Synchronous Sequential circuits

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• Up/down counters
• Shift registers
• Pattern/sequence detectors
• Odd counters like divide by 5 and divide by 3

Finite State machines

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• Mealy state machine
• Moore state machine
• Design examples of Mealy and Moore circuits

• Hierarchy Scopes
• Concurrency
• Reserved Keywords
• Lexical Conventions
• Module Definitions
• Module Port Declarations
• Register, Net and Other Data Types
• Module Instances
• Primitive Instances
• Procedural Blocks

• Timing Controls
• Procedural Assignments
• Programming Statements
• Operators
• Continuous Assignments
• Task Definitions
• Function Definitions
• System Tasks and Functions
• Compiler Directives
• Asynchronous Test bench generation
• Synchronous Test bench generation

MODULE-4: Real Time Projects

• Pci-express Transaction Layer
• SATA Controller
• Ethernet 1G/10G
• Ethernet 10G PCS
• Fiber Channel
• AMBA AHB, APB, MDIO
• MDIO and AHB Bridges
• UART Controller, I2C and SPI bus
• Phase Compensation and Elasticity FIFO
• DDR Controller
• Interlaken
• System packet interface

MODULE-5: Synthesis

• Introduction to synthesis.
• HDL Modeling
• Synthesis flow
• Constraining the design for timing, area, power
• Synthesize the Design Analyze & Debug the results .
• Optimization techniques
• Report generation
• Save the results and generate interface files to other tools

MODULE-6: Static timing analysis

• Introduction to Static Timing Analysis
• Understanding Delays & Libraries:
• Constraining the design with SDC commands.
• Timing Analysis of Different Paths
• Analyzing Timing Reports
• Timing Exceptions:
• Operating Conditions
• Check timing by loading different .libs

MODULE-7: Personality Development Skills

• Improving Communication Skills
• Technical Presentations
• Group Discussions