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  • B.tech/M.tech Project execution
                               
    Category:   Full time
    Duration:     4 months
    Eligibility:    BE/BTECH/ME/MTECH/MSC Electronics/CSE/IT

"Next two batches are starting in the month of July and August"

MODULE-1 : VLSI Flow Basics

  • Overview of VLSI
  • ASIC & FPGA Flow
  • Protocol Highlights
  • Fundamentals of SOC
  • Semiconductor Industry Requirements

MODULE-2 : Digital Logic Design Concepts

Introduction

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  • Analog and Digital signals.
  • Digital circuits v/s Analog circuits

Logic Gates and Combinational Circuits

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  • Truth tables of logic gates & representations
  • Universal logic gates
  • Combining gates to form circuits for simple logic functions.
  • Code Converters
  • Adders, subtractors and carry look ahead adders
  • Multiplexers and design based on multiplexers
  • Encoders and Decoders
  • Parity Generators and Checkers

Sequential Circuits

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  • Latches, Flip-flops
  • JK, SR, D and T Flip flops and conversions
  • Clock, setup time, Hold time
  • Metastability Conditions and preventive actions
  • Memory elements
  • FIFO component

Design of Synchronous Sequential circuits

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  • Up/down counters
  • Shift registers
  • Pattern/sequence detectors
  • Odd counters like divide by 5 and divide by 3

Finite State machines

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  • Mealy state machine
  • Moore state machine
  • Design examples of Mealy and Moore circuits


MODULE-3:Verilog Hardware Description Language

  • Hierarchy Scopes
  • Concurrency
  • Reserved Keywords
  • Lexical Conventions
  • Module Definitions
  • Module Port Declarations
  • Register, Net and Other Data Types
  • Module Instances
  • Primitive Instances
  • Procedural Blocks
  • Timing Controls
  • Procedural Assignments
  • Programming Statements
  • Operators
  • Continuous Assignments
  • Task Definitions
  • Function Definitions
  • System Tasks and Functions
  • Compiler Directives
  • Asynchronous Test bench generation
  • Synchronous Test bench generation

MODULE-4:ASIC Verification Flow and Methodologies

ASIC Verification

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  • What is Functional verification ?
  • What is Gate-level simulation ?
  • Verification Issues
  • ASIC Verification flow

Why verification is important?

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  • Importance of verification
  • Why verification is complex?
  • When is verification complete?

ASIC Verification methodology

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  • Verification environment
  • Verification Terminology
  • Test Bench Design
  • Best Practices
  • Randomization
  • Automation
  • High level languages
  • Methodologies
  • Methodology history
  • Details on different methodologies

ASIC Verification coverage concepts

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  • Functional coverage
  • Code coverage
    • Line Coverage
    • Conditional Coverage
    • Toggle Coverage
    • Expression coverage

MODULE-5: Real Time Projects

  • Pci-express Transaction Layer
  • SATA Controller
  • Ethernet 1G/10G
  • Ethernet 10G PCS
  • Fiber Channel
  • AMBA AHB, APB, MDIO
  • MDIO and AHB Bridges
  • UART Controller, I2C and SPI bus
  • Phase Compensation and Elasticity FIFO
  • DDR Controller
  • Interlaken
  • System packet interface





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